1. Field of Invention
The present invention relates to a display technology of a panel display and, more particularly, to a source driver with charge recycling function.
2. Description of the Prior Art
In recent years, thanks to significant progress and development in display technology, the conventional Cathode-Ray Tube (CRT) displays have been replaced by the so-called panel displays. The most common panel display is TFT-LCD (thin-film transistor liquid crystal display). In addition, Light-Emitting-Diode Display (LED display) and Plasma Display Panel (PDP) are getting more market share day by day.
The display sector of a panel displaying device comprises pixel arrays which, in general, take an arrangement form of matrix with a plurality of line-column intersections, but each pixel is controlled by a driver which drives corresponding pixels based on the image data arranged in arrays.
FIG. 1 is a block diagram showing a source driver of a conventional LCD (Liquid Crystal Display), wherein the pixels are driven by the source driver and a gate driver in an LCD. To correct displayed colors, color calibration data will be input into the source driver. The source driver, as shown, comprises a shift register 100, a line latch 102, a level shifter 104, a DAC 106 (digital-to-analog converter), an output buffer 108, a signal receiver 110 and a data register 112. Wherein the DAC 106 would receive parallel input voltage levels VGMA1˜VGMA14 of the Gamma-Color-Calibration Curve. The signal receiver 110 receives input signals, such as the signals related to RSDS (Reduced Swing Differential Signaling, a type of display interface format). In addition, output signals Y1, Y2, . . . from the output buffer 108 are to drive the pixels for the display purpose. The source driver shown in FIG. 1 is prior art, and should be apparent to those skilled in the art, so is not described in detail herein.
A basic configuration for a conventional LCD is shown in FIG. 2 which includes a TFT-LCD pixel array 120 for displaying an image. Wherein, in the pixel array 120, the line arrays and column arrays are driven by a plurality of source drivers 122 and a plurality of gate drivers 124, respectively; a power unit 130, such as a DC/DC converter, provides voltages to both the source driver 122 and the gate driver 124. In addition, an ASIC chip 126 (application specification integrated circuit chip) generates appropriate clock, control signals and color data etc. corresponding to the data signals required for the output from the source driver 122 and the gate driver 124 (shown as the output arrows in the figure). The required data signals are apparent to those skilled in the art, so are not described in detail herein.
FIG. 3 is a schematic diagram showing the driving mode. As illustrated in FIG. 3, a source driver 210 (122 in FIG. 2) includes an output buffer 212, which is connected to a ground voltage GND and an operation voltage VDD, and provides data lines, such as the data line 206a, 206b, 206c and 206d, with the data signal 208a and 208b for displaying the corresponding pixel 202 in the pixel array 200, wherein four pixels are taken as examples for a simple explanation. A scan line 204 is connected to a pixel line. Any single pixel 202 includes a TFT 202a and a capacitor 202b formed by a liquid crystal capacitor and a storage capacitor connected in parallel. In addition, according to driving mode of image pixels, the data lines are generally divided by data lines with odd number of channel and data lines with even number of channel. These two kinds of data signals provided by the output buffer 212 are AC voltage pulse signals. In terms of their maxim output voltages, these two data signals have waveforms shown as the signal 208a and the signal 208b, indicating a phase difference of 180 degree from each other.
In terms of driving mode, the output buffer 212 must continuously repeat charge/discharge processes between two voltage limits VDD and GND. According to the characteristic of the circuit, the output power of operation amplifier (OP) is:OP=VDD×N×Cload×Vswing×(½)×FH 
Wherein, VDD is the voltage applying to the operation amplifier, N is the total number of data lines, Cload is the load capacitance of data lines, Vswing is the AC voltage swing provided by the operation amplifier for driving data lines, and the AC signals are chosen because the LCD pixels are driven in an AC mode. FH, i.e. horizontal frequency, is reciprocal of a period required for scanning a horizontal line within an image frame. Factor ½ is inducted here because in a period of an AC pulse wave signal, the effective swing voltage occupies only half of a whole period.
FIGS. 4A and 4B illustrate polarity arrangements of pixels in a frame in AC driving mode. In FIG. 4A the adjacent pixels are, for example, driven in different polarities, i.e. in dot inversion driving mode. On the other hand, in FIG. 4B, the pixels in two neighboring columns are, for example, driven in different polarities, i.e. in line inversion driving mode.
For the conventional configuration shown in FIG. 3, the AC voltage swing Vswing of data signals 208a and 208b is very large, therefore the output power of the operation amplifier provided by voltage VDD is also quite large. Also, along with the increasing application of portable display panels in recent years, reducing the panel power has become a bottle neck to be dealt with. Accordingly, how to make the display panel more electricity-saving to reduce the power for driving the panels is one of the important tasks for the manufacturers.